Ettus Research and Xilinx are excited to sponsor The RFNoC & Vivado HLS Challenge. This challenge rewards engineers for creating innovative and useful open-source RF Network on Chip (RFNoC) blocks that highlight the productivity and development advantage of Xilinx® Vivado® High-Level Synthesis (HLS) for FPGA programming using C, C++, or System C. The new RFNoC blocks generated during the challenge will add to the rapidly growing library of available open-source blocks for programming FPGAs in SDR development and production.
For more information on RFNoC click here
For more information on Vivado HLS click here
December 31st, 2016: Proposals due. Closed
January 2017: Proposal acceptance / rejection notices sent out. Closed
March 31, 2017: Progress report due
May / June 2017: Competition, prizes awarded.
Fall 2017: Publication of GRCon Technical Proceedings.
The window for proposals for the RFNoC Vivado HLS Challenge is now closed.
The challenge is open to anyone except employees of Ettus Research/National Instruments, or Xilinx.
You will retain ownership and copyright over all code that you create, and must publish the code online (e.g., Github, Gitlab, etc.,) under the MIT license.
The only exception to this is if during the course of your development you contribute code to another project (e.g., UHD or GNU Radio), in which case you obviously must follow the contributing rules for those projects.
Proposals should be submitted in PDF form, and should be no longer than 1 page in length. Your proposal should include the following information:
- Team name, names of its members, the name of your sponsoring organization if you have one (e.g., your university or company), and contact information.
- A description of the application you intend to create. Try to keep this as simple as possible while providing enough detail to understand the capabilities and flow of data in your application. Feel free to include a block diagram or flowgraph mock-up.
- What new NoC blocks you will create to facilitate this application and each block's function.
- What hardware you anticipate your application needing to operate.
Contest entries will be in the form of complete RFNoC applications, including all blocks required to execute the application and documentation. Newly created RFNoC blocks should be designed in Vivado HLS. Entries must work with the latest tagged release of UHD/RFNoC as of March 2017, and should be compatible with Xilinx Vivado 2015.4.
Examples of interesting applications include, but are not limited to, Direction Finding, MIMO, Signals Detection & Analysis, and 802.11.
Judging will be based on the following criteria:
- Utility of the created NoC Blocks
- How well the blocks perform their intended purpose
- How well the blocks use Vivado HLS
- Overall usability of the RFNoC Application
- Quality of block documentation
Accepted contestants must submit a technical paper for publication to the GRCon17 Technical Proceedings. The paper should outline their contribution design, implementation, results, and lessons learned. Acceptance to the proceedings is up to the GNU Radio Technical Proceedings Committee, and is not influenced by Ettus Research or Xilinx.
Submitt technical papers to the GRCon17 here.
The competition will take place in the May/June 2017 time period, and will consist of a presentation to a panel of judges made up of representatives from Ettus Research and Xilinx. Details and dates of the presentation will be shared once the venue is finalized.
A panel of Ettus Research and Xilinx staff will award prizes to the best submissions.
- Grand Prize: Cash prize up to $10,000
- 2nd Prize: Complete new USRP system of your choice
- 3rd Prize: USRP X310
All winners and additional honorable mentions will receive Ettus Research Swag!
Challenge updates will be sent directly to member teams who have submitted proposals. For any questions related to the RFNoC & Vivado HLS Challenge please contact firstname.lastname@example.org